Mike Ekberg   emike@rloc.com


Professional Objective

I am interested in a medium to long term contract position, in either
application, systems, or tool development, using my 20
years of experience in UNIX, Windows, programming, CAD/ASIC tool
development, web-based applications and management, and networking.


Work Experience
...............

1999-present(Q12001) Sr.Verification Engineer/Director iReady Corp.

Verification engineer/manager/director for a small Internet startup design
and testing hardware implementation of a netwirk stack using TCP/IP/PPP/Ethernet
protocols. Verification/design environment includes NC-Verilog, testbenches,
Verilog and Perl based test files, LSF batch jobs, nightly regression scripts to
run and report simulation.

1997-1999    Sr. Manager, Verification, Silicon Graphics, Inc.

Verification manager for very large workstation graphics accelerator. Drove
concensus for verification strategy for 100+ engineers. Co-managed development
of innovative verification infrastructure, shared w/ another 100+ engineer project.
Managed development of several large semi-custom testbenches at chiplet and chip
level. Managed large-scale  regression tools that run 1000s of tests on nightly 
and weekly basis, website w/ automatic generated results, links to all status files, 
history logging.
Advised on usage of 200+ CPU simulation pool. Wrote various Perl scripts to
condense large reports, improve development environment.

1995-1996       Simulation Lead,  NVIDIA, Inc.

Responsible for continued development of multiple stream, Verilog and
C-based graphics verification environment. Maintained and
modified 2D tests and wrote new 3D tests. Supervised activities of 5 other
verification engineers. Developed plan for integrating 3D verification into 
existing 2D verification environment.
Developed Perl and Makefiles to support running ~1000 graphics verification tests. 
Integrated LSF Queueing manager into verification environment. Recommended and ported HW
development source code control system from SCCS to CVS for concurrent
development. Wrote Verilog bus monitor.

1993-1996       Senior Product Development Engineer,  Cirrus Logic, Inc.

Wrote a clock-cycle accurate C++ simulator for Windows accelerator display
pipeline. Compiled and used GNU C++ compilers and tools. Integrated VHDL-EDIF 
and Mentor schematics, for full-custom layout ASIC using Synopsis scripts and Perl. 
Designed and implemented hierarchical ASIC design source control framework using CVS.
Created wireload models from routed netlists for use by designers during synthesis. 
Developed technique to use Synopsis scripts to create and document metal-only changes 
to design netlist. Member of Cirrus Vice President's CAD Methodology Advisory Committee. 
Improved Window's GUI interface to Winbench performance data extractor.

1989-1993       Hardware Manager 1, Sun Microsystems, Inc.

Managed 9 engineers (2 software, 7 hardware) to develop low-cost OpenWindows
24-bit graphics accelerator. We used Verilog/Synopsis/Motive ASIC design methodology. 
Supervised development of Product Specification, ASIC specification, design,
CAD tools support, and verification. Supervised board development, verification, and 
productization. Wrote a C program to create a Sun rasterfile for visual display of Verilog s
imulated output, as well as several Perl scripts to condense and analyze

Verilog, Synopsis, and Motive results for project.

Previously, my team developed TurboGX, an X11 and 3D wireframe graphics
accelerator. We developed the TurboGX ASIC, an LSI
standard cell 11.2 millimeters on a side, for this project.

Previously, managed the CAD tool and verification groups for a 25 person
effort to design the ZX graphics accelerator. Directly supervised 20 engineers 
developing the simulation/verification environment and microcode for 4 fairly complex 
ASICs in a system using Zycad simulator. Ran the product team meetings for this project, and
was responsible for interfacing with other groups inside of Sun, e,g, compliance and test groups, 
manufacturing, etc.

Previous to that, in December 1990, my team shipped the GS graphics accelerator for SunWindows 
and GPCI, a Sun proprietary API. SunPHIGS and XGL were ported to run on GPCI. Managed 5 
microcode engineers, 5 engineers designing two gate arrays, ran product team meetings, 
interfaced with diagnostic and API porting groups, contract negotiator and technical interface 
with Matrox Corporation, a Canadian graphics company based in Montreal.

1987-1989       Senior Software Engineer, Sun Microsystems, Inc.

Wrote a C simulation for an ASIC that clipped and transformed, for the GX graphics accelerator. 
Work included using tools to trace scan chain in netlist, and Sunview-based simulation output displayer
w/ GUI interface. Wrote a meta-microcode assembler that generated code for 4 different graphics 
pipeline processing elements, using Lex and Yacc Unix tools.

1984-1987       Senior Software Engineer, Weitek, Inc.

Worked on several projects developing high resolution, high speed graphics. First project was a 
68000-based board with custom parallel VLSI graphics chips. The second project was 2901/2910-based 
Multibus board w/ 16 megaflop VLSI. Developed microcode, Unix interface and UNIX device driver 
for Sun II workstation. Ported and extended microcode simulator to UNIX. Added floating
point support to Weitek's RISC assembler. Developed microcode tools using Lex and YACC.

1981-1984       Senior Software Engineer, Androbot, Inc.

I helped design and build a motor control system and remote communication
system for two mobile robots.

1980-1981       Software Engineer, Atari, Inc.

I worked on a disk operating system and RAM-disk accelerator for the Atari 800 OS.

General

B.S. Computer Science, California State University, Chico, 1980.

I have worked on a variety of microprocessors and workstations, including
PDP-11, VAX 780, IBM PC, Atari 800, Sun 2/3/4, 
Sparcstation/UtraSparc, Indigo2/Octane/0rigin2000. 

I have written assembly language for the 6502, 8088/8086, 6809, 8085,
2910/2901,SPARC. I have used Linux, IRIX, SunOS, Solaris, Windows 3.1, Windows 95/98
operating systems.

I have written programs in C++, C, Forth, Basic, FORTRAN, Lisp, Pascal, Perl, Tcl. 
I have created websites, links, created and edited HTML documents. I have done a minor amount of 
Verilog coding, including co-invention of Distributed Verilog PLI code. I have written several 
SunView GUI-based programs. I am proficient in Excel, 123, and Frame. I extended and maintained
Rolo, a public domain rolodex-like Sun View GUI program. I consider myself a Unix
expert. Familiar with EDIF format and netlist translator tools, Mentor schematic design package, Windows GUI, SunView GUI,
X11, HTML, Synopsis.

I have spent 2 years improving and supporting a Verilog simulation environment to test and improve
quality of a hardware implemtation of a network stack of TCP/IP/PPP/Ethernet.

References provided upon request.

Text documented edited 10 Jan 2001.