NAME AND CONTACT INFORMATION:
   Eugene Z Berta
   e_berta@plutospin.com

EDUCATION:
   Carnegie Mellon University, Pittsburgh, PA   
   Degree: Bachelors of Science w/University Honors (5/98) 
   GPA: 3.55 
   Major: Electrical And Computer Engineering
  
WORK EXPERIENCE:
   Software Engineer: Plutospin (Self Funded), Feb 2005- present.
      a) Created a Graphical Programming Interface System (GIPSpin) to 
allow easy coding of threaded applications on both WIN32 and Linux 
systems. See http://www.plutospin.com/gipspin.html for details and 
downloads.
      b) Modified GCC to enable it to output an XML representation of C 
code.
      c) Created a GUI tool to enable users to have unique configuration 
setups for different WiFi hotspots.

   Software/Electrical Engineer:  Hewlett-Packard, June 1998- Jan 2005. 
      a) Worked on the Clock System of the IA-64 McKinley Processor. Was 
lead developer of EZROUTE- a proprietary CAD/GUI tool used to model and 
balance the clock distribution. Responsibilities included CAD/GUI tool 
development for RLC interconnect modeling and delay balancing, design and 
verification of clock logic unit circuitry and distribution, and 
development of load/connectivity verification tools. An ISSCC 2002 paper 
was published on the work: 
http://www.intel.com/design/itanium2/download/isscc_2002_6s.pdf and US 
Patent #6323714 was granted.
      b) Responsible for leading the effort to port and enhance the 
graphics system of our CAD/GUI tools from Starbase to OpenGL/Xlib and also 
assisted with porting and ensuring inter-operability between HPUX and 
LINUX.
      c) Investigated and developed a framework for future statistical
 modeling needs of VLSI timing paths (Patents pending).
      d) Responsible for implementing an incremental timing system for 
VLSI timing paths based on the Pathmill core timing engine.

COURSE WORK:
   Concurrent Real Time Systems: Developed mini-kernel to handle all I/O 
and process handling for an M68000 board with a 4Kbps terminal interface. 
Programmed a multi-threaded "pong" game to test out functionality.

   Superscalar Processor Design: Experimented with a "C code" model of the 
PowerPC RTL to gauge performance versus cost tradeoffs due to increases 
and decreases in functional units such as rename registers, victim 
buffers, pipeline stages, etc.

   Integrated Circuit Design Project: 5-member group project resulting in 
the design of a Hamming 72/64 ECC encoder and decoder chip in a 2um MOSIS 
process. Comprised of around 8K transistors, maximum running speed of 
40MHz.

HARDWARE/SOFTWARE LANGUAGES AND TOOLS:
   Advanced Level:  C, C++, Xlib, Xforms
   Intermediate Level:  Java, SPICE, Matlab, Pathmill, Verilog, Perl, 
80x86 asm, MC68000 asm, Xmotif, SQL, XML, MFC, DDTS, Swing, OpenGL, MPI
   Operating Systems: UNIX, Windows, Linux, HP-UX