Anupam K.


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I develop Operating Systems for Smart Cards, in particular systems for 3G/2G mobile phone based UICC (SIM) cards, and co-design components like the Java Virtual Machine (v2.2) for Smart Cards (SIM/USIM 3G cards). 

This is backed by three years in Simulator Design and Virtual Machine development for RISC Processors, modeling and verification of Chip Core architectures, and benchmarking of new RISC processor ISA families. 

My domain is Embedded Systems Software Development. Currently developing a Secure-OS for mobile-phone cards for clients like NTT and Vodafone, I have also designed cycle-accurate and functional models for RISC processors in C/C++, created random test pattern generator tools in PERL, and simulated and designed IO peripherals for the same System on Chip, in Verilog.

I have working knowledge of Smart Card Operating Systems, of chip/SOC architectures like the Hitachi SH series, the Infineon SLE series, the ARM series, their design structures, and their interfaces with Operating Systems. I also have experience of general tool development in C/PERL/Lex -Yacc

Languages, Scripts, Environment
C, C++, Perl, Assembly, DGL, Lex, YACC, PLI, UNIX Shell scripts, Unix/Win32, Java (JVCM design)

Areas of Expertise
OS design, Functional/Cyclic modeling and verification of RISC processors, Tool Development (Language Translators)
Current Position â?“ Technical Lead / Architect/ OS Developer for 128K Mobile Phone 3G/2G (U) SIM /UICC cards and for EMV based MasterCard Credit/Debit cards. 

Profile description: Worked at the US Texas based Schlumberger Axaltoâ?™s central R&D headquarters in Paris (France) from June 2004 to Present. My job involved baseline OS development, code optimizations for memory/performance, implementing secure algorithms, implementing on-card Java Virtual Machine, product customizations for different clients, and porting on different chip architectures.

Project 1: Product development for Vodafone Group (GUSIM 2008),

Architect for product development (GUSIM 2008) for Vodafone Group, from Schlumberger Systems. Involved in defining and implementing the specifications and architecture of a Vodafone Mobile TV based product called GUSIM 2008, based on standards like MBMS and GBL. Used the baseline OS which I developed for Axalto, beginning June 2004 in France.

Project 2: Native OS development for NTT DoCoMo Product (Japan, FOMA), on an Infineon SLE884000cfxp chip.

Client: NTT DoCoMo (Japan), the 3G/2G FOMA series of mobile UICC cards.

Project Details: Worked in a team of 3, to release a product specific to DoCoMoâ?™s requirements. Specifications included development of standard Java Virtual Machine (compliant to JCVM specs 2.2), Over the Air Protocol (TS 102 223, 23.040, 23.048), and adding NTT specific APDU implementations. Additionally, implemented secure algorithms like the Elliptic Curve Cryptographic algorithm, the Milenage algorithm (French), standard RSA support etc. Adapted memory management to new type of card (Romless, Flash)

Product has been successfully launched and accepted in the Japanese market. Migrated the product for SKT, Korea with proprietary requirements.

Upgrading product by porting previous products on Atmel chip derivatives (256K ROM, 72K EEPROM)

Project 3:  Native OS development for credit/debit cards for French banks. Certified by MasterCard for EMV. High security components (DDA/RSA) implemented on this OS.

Project Location: Beijing, China.

Developed a proprietary OS targeted by Schlumberger for a prototype card to secure MasterCardâ?™s certification.
The product helps in EMV migration of major European merchant banks, starting 2004. 

Role involved Native OS development for EMV, interaction with MasterCard in France, clearing project bottlenecks related to the specification and design, related to the security certification, and memory constraints on the card. Product was successfully implemented and accepted.

Project 4: Native OS development for Smart Card Transport Applications Card for India. (SCOSTA). 
Client: Ministry of Transport (Govt. of India), in collaboration with Indian universities like IIT Delhi/Kanpur.
Tools: C, Chip environment (emulators etc), proprietary smart card tools of Schlumberger.
Role: Working in a team of 4 to design and develop a Smart-Card OS on 4K/8K EEPROM smart cards, compliant to the ISO 7816 smart card specifications. 

My role involved the OS development in Beijing, following this up by porting the OS to different processors (Hitachi, Atmel and Samsung). A parallel aim was to drive this product for the Indian Market, by building communication between Beijing and India, and being involved in specification design with the marketing in India.

Worked as Member Technical Staff and Team Leader, Microprocessor Software Design group.

Project 5: SH-5 Processor Verification (30 months)
Project Location: US (San Jose, California) and India (New Delhi)

This project involved SH-5 RISC processor core development, simulator design and SOC verification at Instructional, functional, architecture and implementation level, for different processor modules of SH-5 during its design phase, along with software development as suitable for chip architecture verification.

The project started from CPU Core development, and extended to development of all IO peripherals of the SOC, like the DMA, Interrupt Controller, Clock, Power and Reset Controller, PCI Interface etc.

Client: The client was SuperH U.S (Renesas), a leading RISC Processor design-house. 
Environment: Unix, C, SH-Assembly, Perl, DGL, and Verilog-C interface (PLI).
Tools: Standard GNU Tool chain (GCC, GDB) along with Hitachi and ST Tool chain (proprietary), Lex, Yacc. 
Role: (Member Technical Staff to Team Leader)
Design Experience 
* Involved in the design of core and coding of the instruction set core simulator (ISS) for SH5. (CPU, Instruction & Data Cache, Bus Interface Unit, Instruction Fetch, Decode and Execute unit). Developed components in C/C++. Some models were also developed using the Verilog-PLI (C interface) mechanism for co-simulation.
* Involved in the design and coding of a mode compatible on-the-fly instruction pipeline execution & reorder unit for different development versions of the SH5 processor. Used compiler code generator strategies in C and Perl.
* Involved in the design and coding of the system on chip peripherals simulator for SH5 (PCI, Serial, DMA, Clock, Power, Debug/JTAG unit). (C/C++)
* Involved in the design and development of a powerful Random Transaction Generator tool used for verification of the complete SH5 SOC. This uses PERL and DGL productions.
* Involved in the benchmark and performance analysis of SH6 using standard benchmarks like SPEC, BDTI and EEMBC, optimizing the assembly code for SH6 using data-dependency analysis, loop unrolling, instruction re-scheduling etc for performance results, writing compiler backend modifications for the same.
* Involved in initiation and ground-blocks for the performance evaluator and simulator of the SH6 core.

Verification Experience
* Developed a PCI-PCI Bridge RTL in C and Verilog. This was used as verification environment for the main core.
* Developed a generic Memory Controller Core for the SH5 (SRAM and SDRAM memories), with Random Transaction Generators, using the C-PLI Interface.
* Developed the SH5 verification environment in the form of C Verification Libraries APIs. 
* Cache Verification: Designed verification test plan and developed template test cases to verify the cache-snoop, cache-replacement, locking and other attributes verification of the cache mechanism of the processor.
* PCI Verification: Designed the verification test plan and developed actual test cases in C to verify the Interrupt-Handling Mechanism and Power State management of the PCI Bridge component of the processor.
* Flash Verification: Designed the verification test plan and developed actual test cases in C to verify the functionality of the Flash Memory Controller (Flash, ROM and MPX) on the SH5 SOC.

Project 6: (Hitachi Semiconductors U.S.)  IPMI Board Design and Verification Project.
Project Brief: The IPMI board was a development board being built by Hitachi Semiconductors to be used with Intel, Dell and IBM Servers, and by OEMs as an IPMI baseboard standard.

Project Location: San Jose California, US
* Involved in Firmware Development for the IPMI (Intelligent Platform Management Interface) Board.
* Involved in FPGA development of a PCI-LPC (Low Pin Count) Bridge on the IPMI Board. 
* Involved in IPMI Board bring-up and IPMI board-debug.
* Involved in generating the Board Technical Description documentation for the IPMI Board.

Project 7: HDL Translator in C/Perl, to convert an HDL (Newt â?“ a proprietary HDL of SGI) to Verilog (standard HDL).  Output Verilog was high quality and synthesizable on DC, Mentor Graphics and standard tools.
Client: Silicon Graphics, US.
Project Location: India
Tools: C, Perl, Lex and Yacc on Linux.
Team Leader in designing the tool architecture and implementation of the language converter. I was responsible for completing the project within a very strict deadline while completely meeting the clientâ?™s requirements.
* Master of Computer Applications, BIT Mesra, Ranchi, India (1997-2000) (University Topper 1997-2000, GPA of 9.2)
* B.Sc. (Hons) (Electronics), South Campus, University of Delhi, India (1994-1997). (GPA of 8.1)

Member number:9732
Additional Contact information is available on the Information Page.
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Copyright(c) 1995 - 2006 Anupam K. and Software Contractors' Guild, 3 Country Club Dr., #303, Manchester, NH USA 03102