Antonio Park

 

 

Objective: Hardware Engineer( ASIC, FPGA, Embedded SoC)

 

 

Highlights of Qualifications:

♦         Over 10 Years Experience in ASIC, FPGA Embedded Hardware Engineering.

♦         BSc Electrical Engineering Degree.

♦         Assisted the Development of patents of LCD Driving and Display Control in USA, Korea, Taiwan

♦         Expertise with ASIC, FPGA SoC(System On Chip)  Embedded System Design Methodology

♦         Strong Experience in ASIC Design in 0.25um,0.18um Technology

♦         Hand On Experience in FPGA’s Design with Xilinx, Altera, Actel

♦         Proven Ability with System Level Design and Verification and Debugging Skills

♦         Strong expertise of board / system Level Design and Verification.

♦         Good communication, organization, analytical and management skills to meet deadline

♦         Strong problem solving ability and an effective team player.

 

 

Design Tools:

 

♦         Xilinx, ISE8.1i, EDK8.1i ,ChipScope8.1i Spartan3, Virtex2pro FPGA	♦         C,VC++, Shell, Perl, VerilogHDL,VHDL, Specman, Matlab
♦         Altera, Quartus2, MAX2 CPLD, FPGA	♦         Synopsys DC, PT, Power Compiler, DFT
♦         Actel, LiberoIDE, ProAsic3	♦         Cadence NCVerilog, HDL Simulator
♦         Pspice, Protel99SE, Orcad, Mentor Boardstation2	♦         Mentor Graphics ModelSim
♦         Numega SoftIce, Windbg,	♦         Unix, Linux, WinCE , Linux
♦         Green Hill RTOS, Wince4.1 OS	♦         Visio, MSOffice

 

 

Professional Experience:

 

Ensil Canada                                            Markham, Canada                    Mar 2007 – Aug 2007

FPGA (SoC) Engineer   

♦         Implemented top modules with ML-SD-1553, Hotlink, SDC, UART Serial interface in Xilinx EDK  

♦         Simulated IP Cores with VHDL Testbench and Analyzed timing issues with military specification.

♦         Redesigned the EMC(External Memory Controller) for SRAM, Flash.

♦         VHDL, C, ModelSim XE, Xilinx (EDK8.2i, ISE8.2i, Chipscope8.2i).

 

PEC Technologies,                                     Richmond Hill, Canada                Apr 2005 – Dec 2006

ASIC Engineer  

♦         Verified the RTL  for 1.3M Image sensor Interfacing with Modelsim_v5.5f for 90nm Technologies

♦         Researched MIPI(Mobile industry processor interface) standard protocols for CCD, LCD.

♦         Researched 2D/3D Graphic processing for simple graphic PIP with Video input.

♦         VerilogHDL, ModelSim5.5f, Matlab6.0, Synplify

 

Nexgtelecom                                               Seoul, Korea                               Jan 2004 – Mar 2005

ASIC/ FPGA  Engineer

♦         Implemented behavioral model & Algorithms of the OCR(Optical Character Recognition)  including Image Skew Correction, Adaptive Binary, Auto Focusing, Auto Exposure, Auto White Balance.

♦         Designed SoC Architectures based Fujitsu Platform; ARM946E CPU and Bus(AHB,APB), MPMC, DMA, Memory Plan, Decision of SW and HW boundary,

♦         Verified the timing and full chip functions for mobile phone display targeted Fujitsu 0.18um ASIC Technology and library with Pre/Post Layout Simulation and Synthesis and Test Vector Generation, Power Estimation

♦         Supported the emulation of all functions in FPGA and Timing Analysis; Image sensor processor, Scaling, Zooming, JPEG Encoding/Decoding, LCD Serial Interface, Color Conversion, DMA Controller with PSRAM, Gamma Correction, Dithering

♦         VerilogHDL ModelSim, NCVerilog, Matlab, Synopsys Design Compiler, Xilinx ISE Virtex4 

 

JASTEC CO.LTD                                              Seoul, Korea                            Apr 2002 – Dec 2003

FPGA Engineer

♦         Maintained USB, Serial, PS, WinCE4.x, Linux Device Drivers for Touch Screen Controller

♦         Configured and Ported RTOS ,WINCE4.0 and supported Firmware Programs and User application Programs for GM-DAEWOO Auto-Scan Tools based on S3C2410, ARM7 Embedded CPU

♦         Implemented Bus Interface and LCD Controller with ACTEL ProASIC FPGA for LCD Panel Test Equipments and simulated and Synthesis with Xilinx ISE EDA.

♦         VerilogHDL, Xilinx ISE Foundation, Actel FPGA,, Numega SoftIce, Windbg, Pspice, Protel99SE, Orcad, Wince4.0 OS

 

ATI Technologies                                              Markham, Canada                 Apr 2001 – Apr 2002

Senior ASIC Engineer

♦         Verified PCI Host Data Path, Video Format, Video Encoding Blocks to check the Timing and Functions of the Graphic Chip targeted 0.18um TSMC ASIC Technology and Library

♦         Checked the Fault Coverage for all assigned blocks with DFT Compiler

♦         C/C++, VHDL, VerilogHDL, Perl,  Sirocco / ModelSim / VCS Simulator,  Synopsys Design/Prime Time/Test Compiler

 

Samsung                                                           Kiheung, Korea                    Sept 1996 – Feb 2001

ASIC/FPGA  Engineer

♦         Designed the RTL Codes for image Scaling processing ASIC Chips including Gamma, Color conversion, Scaling, Dithering ,Timing Recovery, Multi-Clock Synchronization, Multi-Sync Synchronization Targeted 0.25um Samsung ASIC Technologies and Libraries

♦         Performed DFT including Clock Tree Synthesis, Floor-Planning, Post layout Simulation for the Timing Analysis of design Blocks

♦         Emulated Full Chip Functions of Scaling, Frame Rate Conversion, De-Interlacing with Altera CPLD( Flex 10K )  

♦         Designed FPGA with Altera for Timing controller of Panel Display of LCD Monitor, LCD TV, GPS, Navigation, Laptop Display Systems

♦         Designed the circuits of the LCD Control Module, PCB Design, Testing for prototype LCD Display System.

♦         VerilogHDL, C/VC++, Matlab, NCSim, Synopsys Design Compiler, SADAS(Floor-plan), Altera MaxpLus2, Mentor Boardstation, Protel, OrCAD, PSpice, Hspice.

 

Education:

 

Kon-Kuk University

B.Sc., Electrical Engineering

 

Affiliation and Patents:

 

♦         IDEC – Integrated Chip Design and Education Centre – Active Member

♦         Patents Regarding LCD Display Control in USA, Korea – 6 Papers