12910 464th Avenue SE
                                           North Bend, WA 98045
  
                                           Home/Work: (425) 888-5276
                                           Email: vlsi@centurytel.net


                           Steve Martin

Work Experience:

February 1999-present       VLSI Consulting              North Bend, WA
                            Contractor – sole proprietor
                    
   ·  FPGA Design, Synthesis, Verification: Zilog Corp., 3/19/01-present

   Responsible for converting portions of a preliminary ASIC design into a 
   Xilinx Virtex family FPGA for use in a development system.  Tasks 
   include Verilog RTL re-design of a memory arbiter, FPGA device 
   selection and pinout, synthesis, layout, RTL and gate level simulation, 
   and timing analysis.  Tools used include Modelsim, Leonardo Spectrum 
   for synthesis, and Xilinx Alliance for place and route.
    
   ·  Verification for XBOX Game Controller ASIC: Microsoft, 6/1/00-6/1/01

   Worked with another consultant to develop a documented Test Plan for 
   testing a full-speed USB XBOX game controller ASIC. Co-created a 
   Verilog self-checking testbench complete with models for all ASIC 
   interfaces. Wrote tests in both assembly language and Verilog to 
   implement all tests in the Test Plan.
   Responsible for USB Hub, USB full-speed Device, and A2D interface tests.  
   Maintained problem log to track bug fixes.
    
   ·  ASIC Design Engineer, optical USB/PS2 mouse: Microsoft,3/1/00-6/1/00

   Designed the PS2 protocol engine, USB/PS2 detection circuitry, USB 
   interface logic, button detection, motion count generation using 
   Verilog HDL. Provided detailed documentation for all modules to 
   facilitate design re-use.
    
   ·  ASIC Design Engineer,personal input device: Microsoft,9/1/99-1/31/00

   Responsible for the implementation of a microprocessor-based  battery 
   powered ASIC.   Design responsibilities included the Verilog 
   specification and implementation of  the full-speed USB microprocessor
   interface, the Real-Time  clock, PWM module, Quadrature Encoder, Port 
   controllers, LCD controller,  and test controller.  Project cancelled 
   before full chip integration achieved.
    
   ·  ASIC Design Engineer on USB ball mouse: Microsoft, 2/15/99-9/1/99

   Involved in CAD tool selection, USB Device core selection, ASIC vendor 
   selection, and  ASIC specification. Developed expertise in USB 1.1 
   protocol and implementation.   Designed the low-speed USB interface, 
   the clock/reset module and other miscellaneous  functions all using 
   Verilog RTL.  Responsible for chip-level integration, synthesis, and 
   verification.  Responsible for ASIC signoff tasks.    Supported EVT 
   and DVT test plans.  Supported project through production release. 
    
1989-1999             LSI Logic Corporation               Issaquah, WA
                      Senior Field Design Engineer
 
   ·  ASIC Project Management
 
   Senior engineer selected to support major accounts nationwide. Provide 
   technical customer support throughout all phases of the design. 
   Supported  over 100 ASIC designs with companies including Siemens, 
   Compaq, HP, Apple, and Microsoft.
 
   ·  Responsibilities

   Provide Sales support: presentations, travel, conference calls, 
   architectural design partitioning, diesize and power estimation, 
   package selection, statements of work. Support all facets of the 
   customer design flow from presales to production test. Provide 
   customers sub-micron design and test methodology, technology support,
   and signoff guidelines required to guarantee working silicon designed 
   to strict timing specifications. Additional design services provided 
   for customers include: scan insertion, ATPG, PLL testing, package 
   bonding, floorplanning, layout, static timing analysis, power analysis,
   signal integrity, VHDL and Verilog coding, synthesis, simulation, 
   verification. Maintain SUNOS computer network and load and handle all 
   software installations, updates, and licensing issues.

   ·  Major Accomplishments

  Co-designer of MPEG Audio turnkey ASIC using VHDL Responsible for 
  modifying LSI’s existing MPEG audio core and designing the I2C host 
  interface.  Assisted with system level verification.
  Lead application engineer for a mixed-signal ASIC containing 16 8-bit 
  Flash A/D cores and roughly 300K gates.
  Lead application engineer on 1.3 million gate design with Compaq 
  Received Engineering Excellence Award with financial bonus for support 
  effort.                
    
Software Skills:

  Familiar with Solaris, Windows NT, Windows 2000 and Windows98 OS  
  Trained and proficient using both Verilog HDL and VHDL.   
  Shell and PERL scripting languages.
                    
Vendor Specific Software Tools: 

  LSI Logic -- Flexstream  
  Mentor Graphics – Renoir,Leonardo Spectrum,ModelSim,FastScan, DFT Advisor  
  Synopsys -- VSS,DesignCompiler, PrimeTime  
  Cadence--Verilog-XL
  Xilinx - Foundation, Alliance 
 
Education:

  1985-1989       University of Washington              Seattle, WA
                  B.S.E.E., Magna Cum Laude, Phi Beta Kappa,  3.77 G.P.A 
                   
Other Interests: 
               
   Travel, skiing, climbing, mountain biking, rafting, reading.