Randall J. McDonald

74 Jefferson Rd.

Franklin, MA 02038

Home Phone (508) 541-4646

E-mail:  rjmcdonald@tristardes.com

 

 

Professional Summary

 

Experience includes analog and digital design, product development and project management.  Previous 15-years spent providing consulting/contract services for a variety of high technology companies.  Products include voice, T1, T3, E1, SONET, Gig-E, 802.16a and Network Synchronization cards.  Expertise includes high density board development, FPGA/CPLD design (Altera and Xilinx), Verilog code development, PLL design, power supply design and safety and compliance design.  Considerable experience in data communication hardware board design and system architecture. 

 

Technical Skills Summary

 

 

High-Speed Board Development:  1 � 10 GHz board design, termination and signal route analysis.  Hyperlynx signal integrity and timing analysis.

 

Embedded Board Development:  PowerPC, 405GP, MPC860, MPC8270, SRAM, SDRAM, DDR, DDR2

 

Programmable Device Development:  Verilog code development.  Xilinx Virtex-2, Altera EPF10K30, Lattice ispLSI3256, Agere 2C26A

 

Analog Design:  PLL design, development and analysis.  Power supply development and analysis.

 

Compliance:  FCC Part 68 and UL1950/GR-1089 design and compliance testing.  GR-1244 network synchronization design and compliance testing.

 

System Analysis and Architecture:  Network synchronization product architecture and development, automatic protection switching (APS) architecture and development, data path system architecture and development.

 

Project Management:  Project manager for a number of development projects. Responsible for staffing, scheduling and status of hardware, software and mechanical design teams.

 

Tools:  Mentor Graphics DxDesigner, ModelSim, HyperLynx, Cadence Composer, Verilog, Xilinx Foundation.

 

Professional Experience

 

 

Tri-Star Design, Inc.                                                                  September 1991 to Present

Principal Hardware Engineer

 

Tri-Star Design, Inc. provides hardware, software and mechanical consulting services to the North American high technology industry.

 

·   Designed and debugged several OC48, OC12 and OC3 SONET cards for a number of clients and provided SONET compliance services.  Applications included STS switch, ATM and POS products.  Designs included optical transceivers, SERDES interface, SONET framers, STS switching devices and PLL Network Synchronization circuits and a variety of embedded processors and FPGA devices.  Device technology includes PMC, AMCC, Maxim/Dallas, Vitesse and Agere devices.

 

·   Debugged Gig-E cards for a Layer 2 switching product.  Design included Broadcom BCM5693 Layer 2 switch, PMC 1636A Ethernet SERDES devices and MPC8270 processor.  Project involved analyzing and correcting a number of design problems associated with client�s product.

 

·   Performed design analysis on client�s Fabric Switch card set.  Objective of project was to identify specific outdated technologies and provide more cost-effective/reliable design alternatives.  Design included a variety of MMC Fabric Switch/Control devices, PowerPC 405GP processor, SDRAM, 0 buffer delay PLLs and a number of bus transceivers.

 

·   Performed signal integrity design verification testing to 1 � 10 GHz Bit Error Rate Test (BERT) board.  Project included corner testing and providing circuit change recommendations to client. 

 

·   Architected and designed Network Synchronization Timing Cards for a variety of SONET and T1 products.  Designs included BITS interface, composite timing interface, redundancy control logic, Stratum III PLL design and system PLL design.  Device technology includes Connor Winfield, TeraSync, Agere and Vectron International Timing Modules and PLLs.  Architectures required system bandwidth analysis in order to meet specific hitless and errorless performance criteria.

 

·   Provided GR-1244 and GR-253 Network Synchronization consulting services and compliance testing.  Testing included all MTIE/TDEV, wander, jitter and holdover requirements as set forth by the GR-1244 and GR-253 standards.

 

·   Designed 128-channel HDLC/DS0A FPGA for a quad T1 Frame Relay Switch card.  Design converted Siemens Munich 20320 HDLC controller device to handle sub-rate division multiplexer speeds.

 

·   Designed single channel and multi-channel  T1 and E1 cards for TDM, ATM and packet based products.  Designs included all circuitry associated with long haul FCC Part 68/UL1950 and short haul DSX-1 interfaces and redundancy control logic, T1/E1 framers, DS0 switching devices, Bit Error Rate Testing (BERT) devices and circuit emulation switching devices.  Device technology includes PMC, Dallas/Maxim, Zarlink (Mitel), and Exar.

 

·   Designed DS3 cards for TDM, ATM and packet based products.  Designs included DS3 line interface, DS3 framers, circuit emulation devices, M13 devices and redundancy control logic.  Device technology includes PMC, Dallas/Maxim,  Exar and Transwitch.

 

·   Designed Ground Start/ Loop Start PCM Voice cards for T1 product.  Designed all the circuitry necessary to connect to a subscriber loop 2-W interface and encode both voice and signaling bits across a TDM T1 backplane.  Designs included SLIC subscriber interface, PCM encoders and DS0 switching devices.  Design technology included Mitel (Zarlink) Semiconductor devices.   

 

 

·   Designed Basic Rate ISDN U-Interface card.  Designed both S/T and U-interface circuitry for connection to Basic Rate ISDN network.  Design technology included Siemens S/T and U-interface devices.

 

·   Architected 256-channel HDLC controller and M13/E13 multiplexer ASIC.  Provided architectural specifications to Dallas Semiconductor in joint development project.  Design includes the DS3134 256-channel HDLC controller and the DS3120 M13/E13 multiplexer.

 

 

 

Coral Networks, Inc.                                                              January 1990 to August 1991

Senior Hardware Engineer

 

 

·   Responsible for the design and development of a 4-port T1 card.  Card was responsible for encoding packet and circuit T1 data across a proprietary high speed backplane.  Technology included PLL clock recovery circuits, T1 interface and HDLC and DMA controllers.

 

Bytex Corporation                                                                 January 1985 to January 1990

Senior Hardware Engineer

 

·   Designed a 1.5 micron standard cell ASIC for a T1 Interface card.  Design provides the necessary interface to encode circuit data from a T1 multiplexer to the Bytex AS4000 matrix switch.

 

·   Designed and developed an X.21 Port card.  Card provides the Bytex AS4000 matrix switch with access to the X.21 public switch network.

 

·   Designed and developed a PCM Analog port card.  Analog Port card encodes voice frequency analog signals from a 4-wire leased line interface to a TDM bus.

 

·   Designed and developed a T1/E1 Interface card for a time division multiplexer.  Design was responsible for rate adapting and encoding T1/E1 data across a TDM bus.  Design included PLL clock recovery circuits and proprietary clock and data encoding circuits.

 

CODEX Corporation (Motorola)                                            April 1981 to January 1985

Hardware Engineer

 

·   Designed and developed a CVSD and PCM Voice card for the Codex 6240 T1 multiplexer.  Product encoded voice and associated signaling bits onto the 6240 TDM bus.

 

·   Designed and developed a 6^th order passive filter used to simulate the attenuation and delay characteristics of D-conditioned lines.

 

·   Designed and developed a SF Central Office Simulator.  Design included a subscriber loop interface, 2W to 4W hybrid and C-message weighted line simulator.

 

 

Education

 

Northeastern University                                                                     1982

Bachelor of Science in Electrical Engineering